1. Field of the Invention
The present invention relates to a synchronizing circuit and a controlling method of the synchronizing circuit, and particularly to a synchronizing circuit and a controlling method of the synchronizing circuit that can improve performance of a receiving device receiving a modulated signal resulting from digital modulation, for example.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional carrier frequency/phase synchronizing circuit based on a digital PLL (Phase Locked Loop).
Incidentally, suppose in this case that an input symbol (IQ signal) input to the carrier frequency/phase synchronizing circuit of FIG. 1 has a carrier frequency error and a phase error.
An IQ rotating unit 11 rotates the phase of the input symbol so as to correct a signal of a phase from an NCO (Numerically Controlled Oscillator) 15 to be described later according to the signal of the phase. The IQ rotating unit 11 then supplies the input symbol after the phase rotation to a phase calculating unit 12.
The phase calculating unit 12 calculates an argument of the input symbol supplied from the IQ rotating unit 11, and then supplies the argument to a phase error estimating unit 13.
The phase error estimating unit 13 estimates a phase error θn of the input symbol from the argument supplied from the phase calculating unit 12, and then outputs the phase error θn to a loop filter 14.
As to the phase error θn, in a case of a known symbol, which is a symbol whose argument is already known, in for example a frame header or a pilot signal forming a frame, a phase difference between the known symbol and an ideal signal point of the known symbol is output as the phase error θn. In addition, a modulated main signal symbol is judged by hard decision to be at a signal point according to a signal constellation of the main signal symbol, and a phase difference between the main signal symbol and an ideal signal point of the main signal symbol is output as the phase error θn.
The loop filter 14 includes an amplifier 21, an amplifier 22, an arithmetic unit 23, a register 24, and an arithmetic unit 25. The loop filter 14 filters the phase error θn supplied from the phase error estimating unit 13, and controls the NCO 15 to be described later according to a result of the filtering.
Specifically, in the loop filter 14, the phase error θn is multiplied by a loop gain g1 and a loop gain g2 by the amplifier 21 and the amplifier 22, and a resulting value is added to the register 24. Then, a sum of an output value of the register 24 and a value obtained by multiplying the phase error θn by only the loop gain g1 by the amplifier 21 is output as a phase correction quantity. Incidentally, the output value of the register 24 converges to a value (estimated frequency error) corresponding to the frequency error of the input symbol.
The NCO 15 generates a signal of a predetermined phase according to the output from the loop filter 14. The NCO 15 then supplies the IQ rotating unit 11 with the signal of the predetermined phase as a signal corresponding to an original signal point (ideal signal point) on an IQ plane of the input symbol.
That is, a receiving device having the carrier frequency/phase synchronizing circuit of FIG. 1 demodulates a modulated signal into a demodulated signal including an I-component in phase with a carrier and a Q-component orthogonal to the carrier by multiplying the modulated signal by the carrier. However, there is generally an error between the carrier used on the receiving side and a carrier used on a transmitting side that transmits the modulated signal. Due to the error, the symbol (input symbol) of the demodulated signal obtained on the receiving side is rotated in the IQ plane defined by an I-axis indicating the I-component and a Q-axis indicating the Q-component.
That is, the receiving device establishes carrier synchronism to compensate for the rotation of the symbol (input symbol) of the demodulated signal as described above. Specifically, for example, in the receiving device, a phase error θn between the signal of the predetermined phase which signal is output by the NCO 15 and the input symbol is detected, and the phase error θn is filtered by the loop filter 14. Then, the NCO 15 is controlled according to a result of the filtering of the loop filter 14, while the phase of the input symbol is rotated so as to correct the phase error θn according to the phase error θn.
Specifically, as shown in FIG. 2 and FIG. 3, the phase error quantity of an input symbol can be expressed on an IQ plane.
Letting sn be an nth input symbol, and rn be an ideal signal point of the nth input symbol, dn is defined as in the following Equation (1). Incidentally, n is a natural number.dn=sn−rn  (1)
The argument of dn corresponds to the detected phase error θn.
In addition, letting Δθ be an amount of phase rotation per symbol due to a frequency error, the relation of the following Equation (2) holds when phase correction is not made.θn+1=θn+Δθ  (2)
That is, as shown in FIG. 2, the phase error of the nth input symbol is θn, the phase error of a following (n+1)th input symbol is θn+Δθ, the phase error of an (n+2)th input symbol is θn+1+Δθ, the phase error of an (n+3)th input symbol is θn+2+Δθ, . . . .
When phase correction is made for a period of m symbols from the (n+1)th symbol in a condition free from a frequency error, the relation of the following Equation (3) holds.θn+m=(1g1)mθn  (3)
In Equation (3), when g1<1, the phase error θn+m eventually converges to 0. The phase pull-in is shown in FIG. 3. In FIG. 3, the phase error θn of the nth input symbol when phase correction is thereafter made for the period of the m symbols from the (n+1)th symbol is phase-rotated to the phase error θn+m of an (n+m)th input symbol.
When the input symbol has a frequency error, Δθ as shown in Equation (2) is added to the phase error θn+m of the (n+m)th input symbol for each symbol. This θn is multiplied by the loop gain g1 and the loop gain g2, and then added to the register 24 within the loop filter 14. Hence, carrier synchronism is established when a value stored in the register 24 balances Δθ.
As compared with a phase error detected from a known symbol, a phase error detected from a PSK (Phase Shift Keying) modulated main signal symbol is low in reliability because there is a fear of the phase error being erroneously detected due to an erroneous estimation of an estimated signal point of the main signal symbol. Accordingly, the present applicant has previously proposed a technique for controlling the loop gains according to the types of these symbols (see Japanese Patent Laid-Open No. 2002-111768, for example).
In the previous proposition, the loop gains are increased for a known symbol of high reliability, and the loop gains are relatively decreased for a main signal symbol of low reliability, whereby the effect of a phase error of higher reliability is increased, and a detected frequency error is made to converge more quickly.
A carrier frequency/phase synchronizing circuit as shown in FIG. 4 is a circuit that realizes a function of controlling the loop gains.
As compared with the carrier frequency/phase synchronizing circuit of FIG. 1, the carrier frequency/phase synchronizing circuit of FIG. 4 is further provided with a gain controlling unit 31. The gain controlling unit 31 controls the loop gain g1 of an amplifier 21 and the loop gain g2 of an amplifier 22 within a loop filter 14.
The control of the loop gain g1 and the loop gain g2 by the gain controlling unit 31 in FIG. 4 will be described in the following with reference to a timing chart of FIG. 5.
The timing chart of FIG. 5 shows a symbol number, which is a number serially given to a known symbol and a main signal symbol, frame information indicating either a section of main signal symbols (main signal section) or a section of known symbols (known section), a selection signal SA for the selection of the loop gains g1 and g2 for the known section and the main signal section, the loop gain g1, and the loop gain g2 in this order from the top of the figure.
A direction of time is a direction of going from a left to a right of FIG. 5. Incidentally, the direction of time is the same in other timing charts to be described later.
In FIG. 5, s is the number of symbols in a main signal section, and t is the number of symbols in a known section. Hence, when a change is made from a known section to a main signal section at an nth symbol, as shown in FIG. 5, a change is made to a next known section at an (n+s)th symbol, and then a change is made to a next main signal section at an (n+s+t)th symbol. The selection signal SA is 0 when the input symbol is a main signal symbol, and is 1 when the input symbol is a known symbol.
As shown in FIG. 5, in the gain controlling unit 31, when the input symbol is a main signal symbol, the selection signal SA is 0. Thus, a selector 41 outputs the loop gain g1 for a main signal section to the amplifier 21, and a selector 42 outputs the loop gain g2 for a main signal section to the amplifier 22. When the input symbol is a known symbol, the selection signal SA is 1. Thus, the selector 41 outputs the loop gain g1 for a known section to the amplifier 21, and the selector 42 outputs the loop gain g2 for a known section to the amplifier 22.
That is, the gain controlling unit 31 changes the loop gains g1 and g2 output to the loop filter 14 from the loop gains g1 and g2 for a main signal section to the loop gains g1 and g2 for a known section or changes the loop gains g1 and g2 output to the loop filter 14 from the loop gains g1 and g2 for a known section to the loop gains g1 and g2 for a main signal section according to the selection signal SA.
As described above, the carrier frequency/phase synchronizing circuit of FIG. 4 controls the loop gains g1 and g2 so as to increase the loop gains for a known symbol of high reliability and conversely relatively decrease the loop gains for a main signal symbol of low reliability.